1. Field of the Invention
This invention relates to a local area network (LAN) switch architecture, and particularly to a high speed LAN switch which combines different bus architectures to provide superior performance in throughput and latency for switching 1 Mbps-155 Mbps LAN traffic.
2. Description of the Prior Art
Prior art LAN switches are based either on a crossbar architecture or on a time division multiplexed bus architecture.
U.S. Pat. No. 5,264,842 to P. A. Franaszek describes switch connections with wait chains. In a multiport communication system requestors for a busy port are enqueued in the wait chains. The connectivity of a crossbar switch is employed to store the wait chains. Elements of the wait chain are modified to provide the right connections; that is, a group of ports are connected by a form of linked list but with the pointers being comprised of connections in the switch itself. These connections are used both for storing the list structure as well as passing information. This concept requires control information to be transmitted from one port to subsequent ports of the switch fabric matrix.
In U.S. Pat. No. 5,179,552 to H.H. J. Chao a knockout switch design is described. The crosspoint matrix switching element for a large packet switch or a non-buffer based statistical multiplexor uses a crossbar matrix network in which the output ports of individual switching elements are partitioned into various groups in order to share routing paths among the elements in any such group. The outputs of each such group are themselves recursively partitioned into a succession of serially connected groups that each provides a decreasing number of outputs until one such output is provided for each corresponding output port of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs. With this method, if more packets than the switch can handle are presented to the "concentrator", the "concentrator" simply "knocks" them out and relies on the error detection and message re-transmission functions of "higher layer software" to re-transmit the discarded data. Reliance on higher layer protocols to detect lost packets and re-transmit them can produce excessive packet latency and session drop-out due to time-outs. In addition, the re-transmission of "knocked-out" packets further contributes to network congestion and can cause additional packets to be knocked out. This method also uses multiple cell buffers, each such buffer adding one cell delay. This is undesirable in a LAN switch environment where minimum packet latency is highly desired.
U.S. Pat. No. 5,197,064 to H.-H. J. Chao describes a distributed modular packet switch employing recursive partitioning. Such a switch utilizes channel grouping to improve overall performance and a crossbar switching fabric that internally distributes contention resolution and filtering functions among the individual switching elements themselves. Output port grouping is applied recursively until one output path is provided for each output port.
U.S. Pat. No. 5,189,665 to J. A. Niehaus et al. discloses a digital crossbar switch designed to facilitate interconnection of up to 8 data ports. The device includes 8 bidirectional ports, each 8 bit wide. Interconnection of the port is controlled by 32 stored control memory locations associated with each port. In the LAN environment, where port densities in the hundreds are common and desirable, the limitation to an 8 port maximum makes this switch un-attractive.
In U.S. Pat. No. 5,404,461 to H. T. Olnowich et al. a broadcast/switching apparatus for executing broadcast/multi-cast transfers over unbuffered asynchronous switching networks is described. The patent teaches a method of transmitting data as unicast, multicast or broadcast packets using an asynchronous approach to resolve either broadcast or multicast contention among input ports. The broadcast/switching apparatus makes connections from any one of the input ports to any one of the output ports, from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously or from any one of the input ports to all output ports simultaneously.
U.S. Pat. No. 5,179,669 to D. V. Peters teaches a multiprocessor interconnection and access arbitration arrangement. The processors in the multiprocessor system are interconnected by a non-blocking communication medium such as a crossbar switch. By an optical link each processor is connected to a dedicated port circuit at the crossbar switch. By an electrical link each port circuit is connected to the crossbar switch. The port circuits are interconnected by a contention medium. Circuitry at each port circuit receives requests for access to the connected processor, prioritizes conflicting requests and grants them sequentially.
This arrangement uses one link between each port of the switch fabric and each attached processor node.
In U.S. Pat. No. 4,845,722 to A. R. Kent et al. a computer interconnect coupler employing crossbar switching is disclosed. The coupler has a set of junctors which are assigned to channel transmitters and channel receivers for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgement code responsive to the incoming message. The requests are grouped into different priority levels and separate but duplicate arbitration logic is used to resolve simultaneous requests within the same priority group. This patent teaches the use of one bi-directional link or two uni-directional links between each port of the crossbar switch and each attached processor node.
U.S. Pat. No. 5,261,059 to W. F. Hedberg et al. describes a crossbar interface for a data communication network. The crossbar interface between a host computer and a crossbar switch employs data buffering using multiple-port RAM devices. The receive and transmit data is clocked into or out of separate serial ports of the RAM, and at the same time a local processor can access the RAM by a random access port, asynchronous to the serial ports, to execute the protocol. The order of storing bursts of data in the multiple-port RAM is defined by a free buffer manager which keeps account on which locations are free. The addresses of these locations are moved to a received list after being used for incoming packets. After the protocol processor has finished with its tasks, these addresses, referred to as burst data descriptors, are moved to a transmit list to await loading of burst data back to the serial registers for clocking out, then when transmitted the descriptors are again entered into the free buffer manager. This patent teaches the use of a dual-port RAM to improve the efficiency of communications between two connected processors.